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Silicon Labs /Series0 /EFM32LG /EFM32LG280F128 /CMU /HFCORECLKDIV

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Interpret as HFCORECLKDIV

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31282724232019161512118743000000000000000000000000000000000000000000 (HFCLK)HFCORECLKDIV0 (HFCORECLKLEDIV)HFCORECLKLEDIV

HFCORECLKDIV=HFCLK

Description

High Frequency Core Clock Division Register

Fields

HFCORECLKDIV

HFCORECLK Divider

0 (HFCLK): HFCORECLK = HFCLK.

1 (HFCLK2): HFCORECLK = HFCLK/2.

2 (HFCLK4): HFCORECLK = HFCLK/4.

3 (HFCLK8): HFCORECLK = HFCLK/8.

4 (HFCLK16): HFCORECLK = HFCLK/16.

5 (HFCLK32): HFCORECLK = HFCLK/32.

6 (HFCLK64): HFCORECLK = HFCLK/64.

7 (HFCLK128): HFCORECLK = HFCLK/128.

8 (HFCLK256): HFCORECLK = HFCLK/256.

9 (HFCLK512): HFCORECLK = HFCLK/512.
HFCORECLKLEDIV

Additional Division Factor For HFCORECLKLE

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data